Issues in Instruction Scheduling

Instruction scheduling is a code reordering transformation that attempts to hide latencies present in modern day microprocessors. Current applications of these microprocessors and the microprocessors themselves present new parameters under which the scheduler must operate. For example, some multiple functional unit processors have partitioned register sets. In some applications, increasing the static size of a program may not be an acceptable tradeoo for gaining improved running time. The interaction between the scheduler and the register allocator can also dramatically aaect the performance of the compiled code. In this thesis we will look at global scheduling techniques that do not replicate code, including scheduling over extended basic blocks. We also look at a replacement to the traditional list scheduler based on the techniques of iterative repair. Finally, we explore the interaction between instruction scheduling and register allocation, and look at ways of combining the two problems.